Lead Digital Verification Engineer – UVM, SystemVerilog

A leading technology recruitment firm in the UK is seeking a Digital Verification Engineer with expertise in I2C, SPI, and a strong understanding of ASIC design flow. The ideal candidate will have hands-on experience with UVM test benches and automating verification flows using Python or Perl. Familiarity with automotive requirements is highly desirable. Competitive compensation and opportunities for growth are offered. #J-18808-Ljbffr