Remote Digital Verification Engineer – SystemVerilOg/UVM Expert

A leading technology firm is offering an exciting opportunity for a Digital Verification Engineer. This remote role involves ensuring the functional correctness of ASIC designs, developing verification environments using SystemVerilog/UVM, and collaborating with design teams. The ideal candidate will have over 7 years of digital verification experience and strong scripting skills in Python or Perl. This position offers a challenging environment that shapes innovative technology while working with world-class teams. #J-18808-Ljbffr